The present invention relates to an integrated power transistor comprising means for reducing thermal stresses.
It is known that one of the main problems affecting integrated bipolar power transistors is direct secondary breakdown (I.sub.S/B). The problem has predominantly thermal causes. Due to the heating of said power transistor, the base-emitter voltage in fact decreases according to a coefficient which depends on the temperature and is in the range of -2 mV/.degree. C. Assuming a constant collector current (I.sub.o) and the above mentioned temperature coefficient of -2 mV/.degree. C., the density of the collector current increases considerably (approximately 10%), causing a localized heating of the power transistor. The increase in the intrinsic temperature is followed by a rapid non-linear increase in said collector current density and by the forming of so-called hot spots which cause meltings in the Al-Si system, with consequent local short circuits in the region between the emitter and the collector of the power transistor and consequently destroy the power transistor itself.
In order to improve the performance of power transistors, some techniques may be adopted to reduce its operating temperature and the thermal gradient on the surface of said power transistors. However, these known techniques are not satisfactory, due to the limitations of the performance of said power transistors, so that all the proposed measures constitute merely a partial solution to the problem of direct secondary breakdown.
A substantial improvement is disclosed in the U.S. patent application Ser. No. 07/135,220, U.S. Pat. No. 4,886,982, in which a power transistor is replaced by a plurality of current mirrors connected in parallel; each of said current mirrors is formed by an output transistor and by a diode with a preset mutual area ratio, so as to obtain an output transistor gain value in the range of 100, while the diode is a stabilizing element which lowers the thermal sensitivity of the collector current of said output transistor.
Each of said current mirrors is driven by a current source.
The reduction factor of the variation of said collector current due to temperature is equal to: EQU 1/(1+.beta./(1+m))
wherein
m=Area of Transistor/Area of Diode
Implementation of the solution described above entails a buried P.sup.+ -type region containing, in an intermediate portion thereof, a buried N.sup.+ -type layer which acts as mirror for the carriers of said current mirror. Such known devices, however, are still susceptible to improvements, especially in order to eliminate the limitation constituted by the low collector-base voltage, which limits the output of the power transistor. An improvement would consist in eliminating the requirement of feeding said current mirrors with perfectly identical collector currents, as this would make the circuit more flexible.
Furthermore, the use of current sources to drive said current mirrors increases the dimensions and complexity of the power transistors described in the above mentioned application, thus leaving room for further improvements from the point of view of further facilitating integration.
In order to produce the above mentioned N.sup.+ -type buried layer, the P.sup.+ -type buried layer must furthermore be opened during the chip production process, thus increasing the manufacture complexity and costs.